Thursday , August 5 2021

AMD EPYC 2nd generation server processors to reach 253 MB of L3 Cache



Next year, AMD wants to launch 7-nm EPYC server processors in Zen 2 architecture, official announcements a month ago. A two-socket-based, two-socket-based 64-core emblem engineering sample has recently been seen in the SiSoftware Sandra test suite database, which reflects the CPU's next technical characteristics.

AMD EPYC Rome

The second-generation AMD EPYC processors consist of eight eight-piece "chiplets" splinters consisting of eight eight modules consisting of eight modules. Each one has eight eight-core and eight-channel DDR4 memory controller and 14 nm I / O chip and a PCI Express 4.0 interface controller. and other peripherals.

AMD EPYC Rome

According to the SiSoftware database log, each "chiplet" will have instantly 32 MB cache in the third level, divided into four Total CCX units. In other words, the L3 cache volume will be Zen / Zen + architecture to Zen 2. The eighth level AMD EPYC third-level cache is 256 MB impressive.

AMD EPYC

With regard to workplace frequencies, 2S1404E2VJUG5_20 / 14_N, the sample shown in SiSoftware can be increased by up to 1.4 GHz at rated speed and 2 GHz in the drive mode. Note that the release of frequency would be 2.35 GHz.


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